1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to a method of manufacturing forming a via structure in a MOSFET Static Random Access Memory (SRAM) cell and the device manufactured thereby.
2. Description of Related Art
U.S. Pat. No. 5,521,113 of Hsue et al. for "Process for Forming a Butting Contact Through a Gate Electrode" shows a method for forming a butting contact through a gate electrode. However, Hsue et al does not show a butt contact between the second and third polysilicon layers.
U.S. Pat. No. 5,422,499 of Manning for "Sixteen Megabit Static Random Access Memory (SRAM) Cell" shows an SRAM cell with a second layer of polysilicon extending over co-planar surfaces in contact with the third polysilicon region that establishes a contact between the TFT drain and the pull down transistor. However, Manning differs from the invention in the configuration of the butting contacts.
U.S. Pat. No. 5,547,892 of Wuu et al. for "Process for Forming Stacked Contacts and Metal Contacts on Static Random Access Memory Having Thin Film Transistors" shows a process for forming a stacked contact for an SRAM device.
As the design rules are reduced for high density memories, the trend is to use the shallow trench isolation process to replace the well known LOCOS (LOCal Oxidation of Silicon) process. A polysilicon via (or Butt-contact structure) has been used for SRAM cell designs. But that approach is hampered by the problem of butt-contact short-circuits to the P-well of a device due to misalignment of the polysilicon gate to active regions or polysilicon_via (or butt-contact) misalignment to the active region.
In the past the VLSI manufacturing process, a problem has existed in that the area of source/drain regions could not be minimized because it was necessary to align the contact hole with the source/drain regions by using a separate masking step and an extra area had to be allocated to compensate for the probability of misalignment.